Chip Architect/Staff ASIC Design Engineer /芯片架构师/


 北京  面议  本科以上  5年以上  社招


 发布于: 2018.01.12  截止到: 2019.01.12  有效天数 364

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1. Responsible for architecture definition according to product specifications;

2. Logic design & implementation by Verilog on module level, and chip integration;

3. Design synthesis, timing analysis, DFT and ATPG;

4. Work closely with backend engineer for chip physical design and tape-out;

5. Work closely with application engineer for chip bring-up, debug and solve problem;

6. Good IC verification skills and solid logic and circuit design knowledge, good communication and problem solving skills;

7. Experience with professional verification tools such as System Verilog, VMM/OVM/UVM or System C/Testbuilder, etc. Good knowledge of Perl and shell programming would be an added advantage.



1. Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and Computer Science;

2. At least 8+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA;

3. Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and Prime Time;

4. Familiar with video/image process algorithm would be an added advantage;

5. Experience of chip volume production;

6. Familiar with FPGA prototyping development;

7. Familiar with mixed signal or SoC design is better;

8. Good written and oral English communication skills.







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